1. Field of the Invention
The present invention relates to a system bus control apparatus, an integrated circuit, and a data processing system that effectively utilize a system bus for realizing an efficient data transfer.
2. Description of Related Art
There has already been known a technique of performing a bus arbitration in order to carry out an efficient data transfer by effectively utilizing a system bus of an LSI, system bus of a personal computer or image processing apparatus, or system bus of various data processing apparatuses. For example, Japanese Unexamined Patent Publication No. 11(1999)-345196 discloses a technique in which an address/data bus is divided into plural bit widths, and among address values for every plural blocks, only the address value of a changed block is transferred. Japanese Unexamined Patent Publication No. 09(1997)-319699 discloses a technique in which a system bus is divided into plural bits and can be asynchronously used. Japanese Unexamined Patent Publication No. 5(1993)-282242 discloses a technique in which a bus is divided into plural bus line units and the bus is used so as to correspond to the data transfer amount to thereby enhance an efficiency of use of the bus. Japanese Unexamined Patent Publication No. 2004-110224 discloses a technique in which a data bus is divided into predetermined bus widths, a right to use the bus is provided to each data bus, and an arbitration is made in such a manner that the right to use the divided bus is issued in response to a data transfer request.
The technique disclosed in Japanese Unexamined Patent Publication No. 11(1999)-345196 can increase transfer speed. The technique disclosed in Japanese Unexamined Patent Publication No. 09(1997)-319699 enables asynchronous transfer. The technique disclosed in Japanese Unexamined Patent Publication No. 5(1993)-282242 can more efficiently use a bus since a bus is divided into plural bus lines. The technique disclosed in Japanese Unexamined Patent Publication No. 2004-110224 enables to use the bus divided, i.e., a half of the bus is used as a transmitter and the other half of the bus is used as a receiver.
However, when a bus width of transfer-requested data is greater than a bus width that is allowed to be used, data transfer is impossible, and hence, the data transfer should be brought into a stand-by condition.
FIG. 13 is a timing chart for explaining a case where the bus width of the transfer-requested data is greater than the bus width that is allowed to be used, and hence, the data transfer is brought in a stand-by condition. The vertical direction of the chart shown in FIG. 13 represents a bus width of a system bus, while the lateral direction of the chart represents a transfer timing. FIG. 13 represents that there are four system buses having a bus width of 8-bit unit. FIG. 13 shows that a bus master A (8-bit) and a bus master B (16-bit) carry out a data transfer from the timing t1 to the timing t8. In this case, the 8-bit bus width is free.
When a transfer request of 16-bit data is issued from a bus master C during the period from the timing t1 to the timing t8, the bus master C should wait to carry out the data transfer until the transfer from the bus master A or bus master B is completed, since there is only an 8-bit free bus width in the system bus. Since a 16-bit free bus width is generated in the system bus after the transfer from the bus master A or B is completed, the bus mater C can transfer the data from the timing t9. In the example shown in FIG. 13, a free bus width corresponding to 32 bits is generated in the system bus after the transfer from the bus master A or B is completed at the timing t9, but a bus width corresponding to 16 bits is used and another bus width corresponding to 16 bits is free.